Already in rls2110 report, the two-band structure is visible both in PDR and NDR, for example on zn2 [0]. That also shows the results from tests with VPP in VM do not have that clear separation into two bands.
Other testbeds generally show the same structure, just with bigger or smaller gap between the bands. The worst case is Taishan [1], while for most Intel testbeds the gap is small enough to not affect trending nor release comparison much.

The current behavior makes it hard for trending [2] to detect anything useful (for non-Intel testbeds).
In the past, we have seen two-band structure as a consequence of non-deterministic worker thread assignment (see CSIT-1750 [3]), so it is possible we can once again fix CSIT code to achieve more deterministic results.

[0] https://s3-docs.fd.io/csit/rls2110/report/vpp_performance_tests/packet_throughput_graphs/vm_vhost-2n-zn2-cx556a.html
[1] https://s3-docs.fd.io/csit/rls2110/report/vpp_performance_tests/packet_throughput_graphs/vm_vhost-3n-tsh-x520.html
[2] https://s3-docs.fd.io/csit/master/trending/trending/vhost-3n-tsh-x520.html
[3] https://jira.fd.io/browse/CSIT-1750