From initial examination it seems the TRex latency data is always empty when the corresponding TG interface is Intel-E810CQ or Intel-E810XXV.
This includes trex test (tg-tg link without VPP) and 3n-snr (where the DUT side has Intel-E822CQ).
Notably, 2n-clx which has Intel-E810CQ only on DUT (and Mellanox-CX556A on TG) does produce latency data. Even Mellanox-CX7VEAT (when limited to 100Gbps) does produce latency data.

When VPP is forced to print packet trace [0] at low load, "fragment id" values look correct, so TRex latency packets are probably generated correctly even on the E810 NICs, but TRex does not see them when they come back.

Possibly, this is an issue with TRex/DPDK/driver integration. In that case, there is no good fix on CSIT side, and we need to wait for newer TRex versions.

[0] https://s3-logs.fd.io/vex-yul-rot-jenkins-1/csit-vpp-perf-verify-master-2n-icx/250/log.html.gz#s1-s1-s1-s1-s1-t1-k3-k7-k1-k1-k1-k5-k14-k2-k1-k1-k1-k1